PCIe

PCI Express (PCIe) technology is the critical high-speed serial bus in servers, due to its high-bandwidth and low-latency characteristics. PCIe architecture is widely used in various hardware interconnects: CPU to GPU, CPU to network interface card (NIC), CPU to accelerator, CPU to SSD, etc..
iPasslabs is the PCIe expert. In June 2025, it officially received approvement from PCI-SIG to become the PCIe Authorized Test lab, provide preliminary compliance test services (Pre Test) for PCIe 1.0 up to the latest generation PCIe 6.0, as well as official compliance test for PCIe 4.0 & 5.0. iPasslabs is also a working committee of the PCI-SIG serial enabling working group and the designated Gold Suite partner for PCI-SIG's quarterly Compliance test workshops.
iPasslabs is dedicated to providing the industry's most comprehensive PCIe testing solutions. In addition to RX, TX, PLL, and PCIe 5.0/6.0 test fixtures, we also offer PCIe protocol analysis service, which is rare in the industry.
Moreover, ensure the integrity of PCIe 6.0 implementations, the compliance test has been expanded to include two new test item: RLM (Ratio of Level Mismatch) and SNDR (Signal-to-Noise and Distortion Ratio). RLM assesses the consistency of voltage levels, ensuring accurate signal transmission. SNDR represents the ratio of the signal power to the combined power of noise and distortion. A higher SNDR value indicates better signal quality with less noise and distortion.

PCIe

The following test summary are iPasslabs provides for PCIe solutions(keep updated):

Test services for PCIe 6.0

Add In Card:
  • PLL Loop Bandwidth
  • Transmitter Jitter
  • PCI Express 6.0 Transmitter Signal Quality
  • PCI Express 6.0 Link Equalization Testing
  • Configuration Space
  • Link and Transaction Layer
  • Lane margining
  • SNDR
  • PLM
System:
  • PCI Express 6.0 Transmitter Signal Quality
  • PCI Express 6.0 Link Equalization Testing
  • Ref Clock
  • Configuration Space
  • Lane margining
  • RLM

Test services for PCIe 5.0

Add In Card:
  • PLL Loop Bandwidth
  • Transmitter Jitter
  • PCI Express 5.0 Transmitter Signal Quality
  • PCI Express 5.0 Link Equalization Testing
  • Configuration Space
  • Link and Transaction Layer
  • Lane margining
  • Interoperability Test (official test needed)
System:
  • PCI Express 5.0 Transmitter Signal Quality
  • PCI Express 5.0 Link Equalization Testing
  • Ref Clock
  • Configuration Space
  • Interoperability Functional Testing
  • Lane margining
  • Interoperability Test (official test needed)
Revision Max Data Rate Encoding Signaling Solutions
PCIe 1.0 (2003) 2.5 GT/s 8b/10b NRZ TX/PLL
PCIe 2.0 (2007) 5.0 GT/s 8b/10b NRZ TX/PLL
PCIe 3.0 (2010) 8.0 GT/s 128b/130b NRZ RX/TX/PLL/Protocol
PCIe 4.0 (2017) 16.0 GT/s 128b/130b NRZ RX/TX/PLL/Protocol
PCIe 5.0 (2019) 32.0 GT/s 128b/130b NRZ RX/TX/PLL/Protocol
PCIe 6.0 (2023) 64.0 GT/s 1b/1b(Flit Mode) PAM4

*the PCIe 5.0 Base Specification is backwards compatible with lower-speed PCIe Base Specifications.

Equipments

TX:

  • Lecroy LABMASTER 10-50ZI-A
  • Tektronix DPO70000SX
  • Keysight UXR70G

Rx:

  • Anritsu MP1900A 32G NRZ BERT
  • Tektronix BERTScope BSX
  • Anritsu MP1900A PAM4 BERT

Equipments

Protocol：

  • Lecroy Summit T516 Protocol Analyzer

    • “The Summit T516 PCI Express (PCIe) 5.0 and Compute Express Link (CXL) Protocol Analyzer, the first protocol analyzer to capture x16 link width at 32GT/s for capturing, recording, and analysis of high performance devices and systems.”

Others：

  • Tektronix MSO6-4G (Clock Measurement)

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