Power Integrity Simulation
 Power Integrity Simulation

 WHY Power Integrity (PI) Simulation?


Reliable power delivery is essential to every high-performance electronic system. Operating voltages are typically supplied through voltage regulator modules (VRMs), while increasingly complex system architectures demand tighter control over voltage ripple, power noise, and voltage stability. Power integrity (PI) analysis enables comprehensive evaluation of the power distribution network (PDN), helping identify voltage drop and noise issues early in the design phase to optimize power performance and ensure system reliability.



 WHAT Benefits of Power Integrity(PI) Simulation?



As power supply voltages continue to shrink and transistor density increases in accordance with Moore’s Law, power distribution network (PDN) design has become a critical aspect of modern electronic systems. Poor PDN performance can result in excessive voltage drop and power noise, compromising system stability and reliability. Power integrity (PI) simulation enables early prediction and optimization of PDN performance, ensuring stable power delivery and meeting power efficiency requirements in electronic products.


 WHEN Do You Need Power Integrity (PI) Analysis?



When product designs incorporate high-current components or high-speed processors with rapid switching activity, power integrity (PI) analysis becomes essential to ensure stable power delivery and reliable system performance. PI simulation is typically conducted through both AC and DC analysis to evaluate power distribution network (PDN) behavior under different operating conditions.



Our simulation testing services and experience sharing:


Taiwan has emerged as a global hub for AI innovation, with major technology companies planning to establish hyperscale data centers across the region. While this growth presents tremendous opportunities, the increasing demand for power has also become a critical challenge.

A significant portion of energy loss in data centers originates from internal power management systems, particularly the Power Distribution Network (PDN). Insufficiently optimized PDN designs can result in excessive power loss, voltage instability, and reduced system efficiency. In hyperscale data centers, even small inefficiencies can accumulate into substantial energy waste, significantly impacting operational costs and overall power consumption.

In extreme cases, poor PDN performance may lead to thermal issues, equipment degradation, and even safety risks. As computing density continues to rise, driven by AI servers and high-performance processors, PDN design becomes increasingly complex. Effective impedance control and power loss reduction are essential to improving energy efficiency and maintaining system reliability.

Higher power consumption also generates additional heat, driving demand for more advanced cooling solutions and further increasing total energy usage. As a result, optimizing PDN performance through professional power integrity (PI) simulation tools has become a critical step in the product development process for many customers.


Product High Speed Interface
Switch •800G/400G/100G/25G Ethernet
Server/Datacenter •PCIe1.0/2.0/3.0/4.0/5.0/6.0 •NVLink •CXL
Desktop/PC •DDR5, LPDDR5/5x, GDDR6/6x •USB4, USB Type A/C •Thunderbolt 5
Notebook/Laptop •HDMI 2.1, •DisplayPort 2.1, eDisplayPort •NVMe
Mobile/Storage •MIPI CSI/DSI D-PHY/C-PHY •MIPI UFS M-PHY •eMMC
Automotive •MIPI A-PHY •1000/100Base-T1, 10Base-T1S, 2.5/5/10Base-T1
Channel Quality Analysis
ØPre-Sim •PCB material loss evaluation •Routing topology evaluation •Channel crosstalk analysis •Design recommendation ØPost-Sim •S-parameter •Eye-diagram •TDR(Time Domain Reflectometry) •COM(Channel Operation Margin)

Pre-Simulation

  • Evaluation of composite panels and selection of different number of layers
  • High-speed topology selection and system feasibility assessment
  • High-speed chip layout planning and trace length evaluation
  • High-speed signal routing/via impedance matching and fan-out optimization
  • Evaluation of I/O drive strength and termination resistor pairing strategies
  • Develop appropriate routing layout constraints for different high-speed signal interfaces.

PI-DC Analysis (also called IR-drop analysis)


PI-DC analysis computes the IR drop (voltage drop), current density, and power loss density in the power supply nets. Using this analysis, it can identify how much current is consumed by IC, connector pins or stitching vias at DC operating conditions. If the power plane has too big voltage drop, the power supply voltage at the IC might fall below the allowed minimum voltage to cause abnormal work.


  • Voltage drop (find hot-spot location)
  • Current density (find copper areas and stitching via with excessive current)
  • DC resistance (measure power plane resistance for critical layout location)
  • Power loss (measure power dissipation on the power and ground nets)
  • Temperature dependent option (consider electrical-thermal co-analysis)



Pre-Simulation

  • High-speed signal layout violation checks (layout rule check)
  • Compliance check before high-speed signal generation drawings are produced.

PI-AC analysis (also called decoupling capacitor optimize analysis)


PI-AC analysis computes the impedance for the IC power planes over a certain frequency range. It can identify whether the PDN provides a low impedance path from the VRM to the IC power pin. Excessive impedance can generate huge power noise, and will pass through the system PDN to power plane when core has input-output switching to let IC fail to work.


  • PDN impedance (measure how much power plane noise ripple)
  • Decoupling capacitor optimization (find cost-effective capacitor combination)
  • PDN transfer impedance (measure how much power noise coupling between two power plane)
  • Power plane resonance analysis (find resonance location that have the potential high field strength)
  • Capacitor loop inductance (qualify whether the capacitor is placed effectively)

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